A single crystal used as a substrate of semiconductor devices is, for example, a silicon single crystal. It is mainly produced by Czochralski Method (referred to as CZ method for short hereafter).
When producing a single crystal by CZ method, for example, an apparatus 1 for producing a single crystal as shown in FIG. 2 is used to produce the single crystal. This apparatus 1 for producing a single crystal has a member for containing and melting a polycrystalline material such as silicon, heat insulating members to insulate heat, and etc. They are installed in a main chamber 2. A pulling chamber 3 extending upwardly is continuously provided from a ceiling portion of the main chamber 2, and a mechanism (not shown) for pulling a single crystal 4 by a wire 5 is provided above it.
In the main chamber 2, a quartz crucible 7 for containing a melted raw material melt 6 and a graphite crucible 8 supporting the quartz crucible 7 are provided, and these crucibles 7 and 8 are supported by a shaft 9 so that they can be rotated and moved upwardly or downwardly by a driving mechanism (not shown). To compensate for decline of the melt level of the raw material melt 6 caused by pulling of the single crystal 4, the driving mechanism for the crucibles 7 and 8 is designed to rise the crucibles 7 and 8 as much as the melt level declines.
And, a graphite heater 10 for melting the raw material is provided so as to surround the crucibles 7 and 8. A heat insulating member 11 is provided outside the graphite heater 10 so as to surround it in order to prevent that the heat from the graphite heater 10 is directly radiated on the main chamber 2.
Moreover, a cooling cylinder 12 to cool a pulled single crystal is provided and at the bottom of it a graphite cylinder 13 is provided. A cooling gas is flowed downward from top through these cylinders so as to cool a pulled single crystal. And a heat insulating material 14 is provided on the outside of the lower end of the graphite cylinder 13 so as to oppose to the raw material melt 6 so that the heat radiation from the surface of the raw material melt 6 is intercepted and the temperature of the surface of the raw material melt 6 is kept.
A polycrystalline material is put in the quartz crucible 7 installed in the apparatus 1 for producing a single crystal as described above, the crucible 7 is heated by the graphite heater 10 to melt the polycrystalline material in the quartz crucible 7. A seed crystal 16 fixed by a seed holder 15 connected with the lower end of the wire 5 is immersed into the raw material melt 6 melted from the polycrystalline material. Thereafter, the single crystal 4 having a desired diameter and quality is grown under the seed crystal 16 by rotating and pulling the seed crystal 16. In this case, after bringing the seed crystal 16 into contact with the raw material melt 6, so-called necking, once forming a neck portion by narrowing the diameter to about 3 mm, is performed, and then, a dislocation-free crystal is pulled by spreading to a desired diameter.
A silicon single crystal produced by the CZ Method is mainly used to produce semiconductor devices. In recent years, semiconductor devices have come to be integrated higher and devices have come to be finer. Because devices have come to be finer, a problem of Grown-in defects introduced during growth of a crystal has become more important.
Hereafter, Grown-in defects will be explained (see FIG. 5).
In a silicon single crystal, when the growth rate of the crystal is relatively high, there exist Grown-in defects such as FPD (Flow Pattern Defect) and COP (Crystal Originated Particle), which are considered due to voids consisting of agglomerated vacancy-type point defects, at a high density over the entire radial direction of the crystal, and the region containing these defects is referred to as V (Vacancy) region. Furthermore, when the growth rate is further lowered, along with lowering of the growth rate, an OSF (Oxidation Induced Stacking Fault) region is generated from the periphery of the crystal as a shape of a ring. When the growth-rate is further lowered, the OSF ring shrinks to the center of the wafer and disappears. When the growth rate is further lowered, there exist defects such as LSEPD (Large Secco Etch Pit Defect) and LFPD (Large Flow Pattern Defect), which are considered due to dislocation loops consisting of agglomerated interstitial silicon atoms at a low density, and the region where these defects exist is referred to as I (Interstitial) region.
In recent years, a region containing no FPD and COP to be generated due to voids as well as no LSEPD and LFPD to be generated due to interstitial silicon atoms has been found between the V region and the I region and outside the OSF ring. The region is referred to as N (Neutral) region. In addition, it has been found that when further classifying N region, there exist Nv region (the region where a lot of vacancies exist) adjacent to the outside of OSF ring and Ni region (the region where a lot of interstitial silicon atoms exist) adjacent to I region, and that when performing thermal oxidation treatment, a lot of oxygen precipitates are generated in the Nv region and little oxygen precipitates are generated in the Ni region.
Furthermore, it has been found that, after thermal oxidation treatment, there exist a region where defects detected by Cu deposition process are particularly generated (hereinafter referred to as Cu deposition defect region) in a portion of the Nv region where oxygen precipitates tend to be generated. And it has been found that the Cu deposition defect region causes deterioration of electric property like oxide dielectric breakdown voltage characteristics.
It is considered that quantity of introduction of these Grown-in defects is determined by a parameter of a value of V/G which is a ratio of a pulling rate (V) and a temperature gradient (G) at the solid-liquid interface (for example, see V. V. Voronkov, Journal of Crystal Growth, 59 (1982) 625-643). Therefore, by controlling a pulling rate and a temperature gradient so that a value of V/G keeps constant, a single crystal occupied by desired defect region or desired defect-free region can be pulled.
For example, it is disclosed that, when a silicon single crystal is pulled, a single crystal occupied by defect-free region (for example, see Japanese Patent Laid-open (Kokai) No. H11-147786), and a single crystal having an OSF ring or nuclei in an OSF ring in the plane of the crystal and gettering property (for example, see Japanese Patent Laid-open (Kokai) No. 2000-44388) are pulled by controlling a value of V/G. Moreover, it is disclosed that a silicon single crystal occupied by I region is pulled by controlling a value of V/G and doping nitrogen (for example, see Japanese Patent Laid-open (Kokai) No. H11-349394), and a single crystal in which a size, density and distribution of defects are uniform is pulled also with doping nitrogen (for example, see Japanese Patent Laid-open (Kokai) No. 2002-57160). Then, from those single crystals produced above, for example, a wafer the whole plane of which is N region with excluding V region and I region, a wafer in which OSF is situated in the periphery, a wafer occupied by N region without Cu deposition defect region or the like can be produced.
However, for example, when a single crystal the whole plane of which is occupied by N region is pulled, distribution of defects is practically examined, a value of V/G including the region is obtained and a single crystal is pulled at the obtained value of V/G. There are many cases that the estimated value of V/G is different from a value of V/G that a single crystal the whole plane of which is N region can be actually obtained. Especially, there are such a case that, although a furnace structure (hot zone: HZ) is prepared so that a temperature gradient G at the solid-liquid interface becomes large in order to increase productivity of a single crystal of desired defect region and/or desired defect-free region by increasing a pulling rate V, a single crystal with desired quality can be pulled only when a pulling rate V is actually set lower than the estimated rate V. As explained above, there is a problem that a precise value of V/G including a desired defect region and/or a desired defect-free region is unknown and it is difficult to obtain efficiently a single crystal with high quality.